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hot swap controller and digital power monitor with soft-start pin preliminary technical data adm1177 rev. prd may 2006 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2006 analog devices, inc. all rights reserved. features allows safe board insertion and removal from a live backplane controls supply voltages from 3.15 v to 14v precision current sense amplifier precision voltage input 12-bit adc for current and voltage readback charge pumped gate drive for external n-fet switch adjustable analog current limit with circuit breaker fast response limits peak fault current automatic retry or latch-off on current fault programmable hot swap timing via timer pin soft-start pin for reference adjustment and programming of initial current ramp rate active-high on pin i 2 c fast mode compliant interface (400 khz max) 10-lead msop package applications power monitoring/power budgeting central office equipment telecommunication and datacommunication equipment pc/servers general description the adm1177 is an integrated hot-swap controller which offers digital current and voltage monitoring via an on-chip 12-bit adc, communicated through an i 2 c interface. an internal current sense amplifier senses voltage across the sense resistor in the power path via the vcc and sense pins. the adm1177 limits the current through this resistor by controlling the gate voltage of an external n-channel fet in the power path, via the gate pin. the sense voltage (and hence the inrush current) is kept below a preset maximum. the adm1177 protects the external fet by limiting the time that it spends with the maximum current running in it. this current limit period is set by the choice of capacitor attached to the timer pin. additionally, the device provides protection from overcurrent events at times after the hot-swap event is complete. in the case of a short-circuit event the current in the sense resistor will exceed an overcurrent trip threshold, and the fet will be switched off immediately by pulling down the gate pin. functional block diagram + - scl i2c 12-bit adc adm1177 v sense vcc sda gnd i adr ss fet drive controller gate on 0 1 + - uv comparator current sense amplifier mux 1.3v a timer figure 1. applications diagram r sense controller adm1177 sense vcc sda scl sda scl 3.15v - 14v p=vi gnd gate n-channel fet on adr timer ss figure 2. a soft-start (ss) pin is also included. this gives the user control over the reference on the current sense amplifier. an internal current source will charge a capacitor on this pin at startup, allowing the user set the profile of the initial current ramp. a voltage can also be driven on this pin to alter the reference. a 12-bit adc can measure the current seen in the sense resistor, and also the supply voltage on the vcc pin. an industry standard i 2 c interface allows a controller to read current and voltage data from the adc. measurements can be initiated by an i 2 c command. alternatively the adc can run continuously and the user can read the latest conversion data whenever it is required. up to 4 unique i 2 c addresses can be created by the way the adr pin is connected. the adm1177 is packaged in a 10-lead msop package.
adm1177 preliminary technical data rev. prd | page 2 of 16 table of contents revision history may 06revision prd: preliminary version
preliminary technical data adm1177 rev. prd | page 3 of 16 adm1177specifications v vcc = 3.15v to 14v, t a = ?40c to +85c, typical values at t a = +25c unless otherwise noted. table 1. parameter min typ max units conditions vcc pin operating voltage range, v vcc 3.15 14 v supply current, i cc 1.6 3 ma undervoltage lockout, v uvlo 2.8 v v vcc rising undervoltage lockout hysteresis, v uvlohyst 25 mv on pin input current, i inon ?100 0 +100 na trip threshold, v onth 1.3 v on rising trip threshold hysteresis, v onhyst 80 mv glitch filter time 3 s ss pin pullup current, i isspu 10 a v ss = 0v to 1v current setting gain, gain ss 10 v/v v ss / v cb . valid until v ss = 1v, then consider the gain as 10. soft-start completion voltage, ss highv 1.3 v ss continues to pull up beyond 1v pullup current, i isspud 100 a under fault sense pin input leakage, i sense ?1 +1 a v sense = v vcc overcurrent fault timing threshold, v octim 85 mv v octrim = (v vcc ? v sense ), fault timing starts on the timer pin overcurrent limit threshold, v lim 90 100 110 mv v lim = (v vcc ? v sense ), closed loop regulation to a current limit fast overcurrent trip threshold, v ocfast 115 mv v ocfast = (v vcc ? v sense ), gate pulldown current turned on gate pin drive voltage, v gate 5 7 10 v v gate ? v vcc , v vcc = 3.15 v drive voltage, v gate 6 8 12 v v gate ? v vcc , v vcc = 5 v drive voltage, v gate 5 7 10 v v gate ? v vcc , v vcc = 13.2 v pullup current 10 12 14 a v gate = 0 v pulldown current 2 ma v gate = 3 v, v vcc > uvlo pulldown current 25 ma v gate = 3 v, v vcc < uvlo timer pin pull-up current (power on reset), i timeruppor ?4 ?5 ?6 a initial cycle, v timer = 1 v pull-up current (fault mode), i timerupfault ?48 ?60 ?72 a during current fault, v timer = 1 v pull-down current (retry mode), i timerdnretry 2 2.5 a after current fault and during a cool-down period on a retry device, v timer = 1 v pull-down current, i timerdn 100 a normal operation, v timer = 1 v trip threshold high, v timerh 1.235 1.3 1.365 v timer rising trip threshold low, v timerl 0.18 0.2 0.22 v timer falling adr pin set address to 00, v adrlowv 0 0.8 v low state set address to 01, r adrlowz 135 150 165 k? resistor to ground state, load pin with specified resistance for 01 decode set address to 10, i adrhighz ?1 +1 a open state, maximum load allowed on adr pin for 10 decode set address to 11, v adrhighv 2 5.5 v high state input current for 11 decode, i adrlow 3 5 a v adr = 2.0 v to 5.5 v input current for 00 decode, i adrhigh ?40 ?22 a v adr = 0 v to 0.8 v
adm1177 preliminary technical data rev. prd | page 4 of 16 parameter min typ max units conditions monitoring accuracy 1 current sense absolute accuracy tbd tbd % v sense = 75 mv ?2.3 +2.2 % v sense = 75 mv, @ 0c to +70c tbd tbd % v sense = 50mv ?2.5 +2.5 % v sense = 50 mv, @ 0c to +70c tbd tbd % v sense = 25mv ?2.8 +2.8 % v sense = 25mv, @ 0c to +70c ?3.5 +3.5 % v sense = 12.5 mv, @ 25c current sense accuracy, t c 0.01 %/c v sense for adc full-scale 105 mv voltage sense accuracy ?1.5 0 +1.5 % v vcc = 3.0 v to 5.5v(vrange = 1) ?1.5 0 +1.5 % v vcc = 10.8 v to 13.2v(vrange = 0) v cc for adc full-scale, low range 6.656 v vrange = 1 v cc for adc full-scale, high range 26.628 2 v vrange = 0 i 2 c timing 3 low level input voltage, v il 0.99 v high level input voltage, v ih 2.31 v low level output voltage on sda, v ol 0.4 v i ol = 3ma output fall time on sda from v ihmin to v ilmax 20+0.1c b 250 ns c b = bus capacitance from sda to gnd maximum width of spikes suppressed by input filtering on sda and scl pins 50 250 ns input current, i i , on sda/scl when not driving out a logic low ?10 +10 a input capacitance on sda/scl 5 pf scl clock frequency, f scl 400 khz low period of the scl clock 600 ns high period of the scl clock 1300 ns setup time for a repeated start condition, t su;sta 600 ns sda output data hold time, t hd;dat 100 ns set-up time for a stop condition, t su;sto 600 ns bus free time between a stop and a start condition, t buf 1300 ns capacitive load for each bus line 400 pf 1 monitoring accuracy is a measure of the er ror in a code that is read back for a pa rticular voltage/current. this is a combinat ion of amplifier error, reference error and adc error. 2 the maximum operating voltage is limited to v vcc =14 v which corresponds to an adc code of 871. 3 the following conditions apply to all timing specifications: v bus =3.3v, t a =25c. all timings refer to v ihmin and v ilmax .
preliminary technical data adm1177 rev. prd | page 5 of 16 absolute maximum ratings table 2. parameter rating v cc pin 20 v sense pin 20 v timer pin ?0.3 v to +6 v on pin ?0.3 v to +20 v ss pin tbd gate pin 30 v sda, scl pins ?0.3 v to +6 v adr pin ?0.3 v to +6 v power dissipation tbd storage temperature ?65c to +125c operating temperature range ?40c to +85c lead temperature range (soldering 10 sec) 300c junction temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only. functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions may affect device reliability. ambient temperature = 25c, unless otherwise noted. esd (electrostatic discharge) sensitive device. electrosta tic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge with out detection. although this product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
adm1177 preliminary technical data rev. prd | page 6 of 16 pin configurations 1 2 3 4 adm1177 top view (not to scale) vcc adr sda gate on timer sense ss gnd 5 scl 10 9 8 7 6 figure 3. pin configurations pin functional descriptions table 3. pin no. name description 1 vcc positive supply input pin. the operating supply voltage range is between 3.15 v to 14 v. an undervoltage lockout (uvlo) circuit resets the adm1177 when a low supply voltage is detected. 2 sense current sense input pin. a sense resistor between the vcc and sense pins sets the analog current limit. the hotswap operation of the adm1177 controls the external fet gate to maintain the (v vcc -v sense ) voltage at 100 mv or below. 3 on undervoltage input pin. active high pin. an internal on comparator has a trip threshold of 1.3 v and the output of this comparator is used as an enable for the hotswap operation. with an external resistor divider from vcc to gnd, this pin can be used to enable the hotswap operation one a specific voltage on vcc, giving an undervoltage function. 4 gnd chip ground pin 5 timer timer pin. an external capacitor ctimer sets a 270 ms/f initial timing cycle delay and a 21.7 ms/f fault delay. the gate pin turns off whenever the timer pin is pulled beyond the upper threshold. an overvoltage detection with an external zener can be used to force this pin high. 6 scl i 2 c clock pin. open-drain output requir es an external resistive pull-up. 7 sda i 2 c data i/o pin. open-drain output requires an external resistive pull-up. 8 adr i 2 c address pin. this pin can be tied low, tied high, left floating or tied low through a resistor to set four different i 2 c addresses. 9 ss soft-start pin. this pin controls the reference on the current sense amplifier. a 10 a current source charges this pin at startup. a capacitor on this pin will then set the slope of the initial current ramp. this pin can also be driven to a voltage to alter the reference directly, thereby adjusting the current limit level. 10 gate gate output pin. this pin is the high side gate drive of an external n-channel fet. this pin is driven by the fet drive controller which utilises a charge pump to provid e a 12 a pull-up current to charge the fet gate pin. the fet drive controller regulates to a maximum load current (100 mv through the sense resistor) by modulating the gate pin.
preliminary technical data adm1177 rev. prd | page 7 of 16 overview of the hotswap function when circuit boards are inserted into a live backplane, discharged supply bypass capacitors would draw large transient currents from the backplane power bus as they charge. such transient currents can cause permanent damage to connector pins, and dips on the backplane supply which could reset other boards in the system. the adm1177 is designed to turn a circuit boards supply voltage on and off in a controlled manner, allowing the circuit board to be safely inserted into or removed from a live backplane. the adm1177 can reside either on the backplane or on the circuit board itself. the adm1177 controls the inrush current to a fixed maximum level by modulating the gate of an external n- channel fet placed between the live supply rail and the load. this hotswap function protects the card connectors and the fet itself from damage and also limits any problems which could be caused by the high current loads on the live supply rail. the adm1177 holds the gate pin down (and thus the fet is held off) until a number of conditions are met. an undervoltage lockout circuit ensures that the device is being provided with an adequate input supply voltage. once this has been successfully detected, the device goes through an initial timing cycle to provide a delay before it will attempt to hotswap. this delay ensures that the board is fully seated in the backplane before the board is powered up. once the initial timing cycle is complete, the hotswap function is switched on under control of the on pin. when asserted high the hotswap operation starts. the adm1177 charges up the gate of the fet to turn on the load. it will continue to charge up the gate pin until the linear current limit (set to 100 mv/r sense ) is reached. for some combinations of low load capacitance and high current limit, this limit may not be reached before the load is fully charged up. if current limit is reached, the adm1177 will regulate the gate pin to keep the current at this limit. for currents above the overcurrent fault timing threshold, nominally 100 mv/ r sense , the current fault is timed by sourcing a current out to the timer pin. if the load becomes fully charged before the fault current limit time is reached (when the timer pin reaches 1.3 v), the current will drop below the overcurrent fault timing threshold, the adm1177 will then charge the gate pin higher to fully enhance the fet for lowest r on , and the timer pin will be pulled down again. if the fault current limit time is reached before the load drops below the current limit, a fault has been detected, and the hotswap operation is aborted by pulling down on the gate pin to turn off the fet. the adm1177-2 latches off at this point and will only attempt to hotswap again when the on pin is de- asserted then asserted again. the adm1177-1 will retry the hotswap operation indefinitely, keeping the fet in soa by using the timer pin to time a cool-down period in between hotswap attempts. the current and voltage threshold combinations on the timer pin set the retry duty cycle to 3.8%. the adm1177 is designed to operate over a range of supplies from 3.15 v to 14 v. undervoltage lockout an internal undervoltage lockout (uvlo) circuit resets the adm1177 if the vcc supply is too low for normal operation. the uvlo has a low-to-high threshold of 2.8 v, with 25 mv hysteresis. above 2.8 v supply voltage, the adm1177 will start the initial timing cycle. on function the adm1177-1 has an active-high on pin. the on pin is the input to a comparator which has a low-to-high threshold of 1.3 v, an 80 mv hysteresis and a glitch filter of 3 s. a low input on the on pin turns off the hotswap operation by pulling the gate pin to ground, turning off the external fet. the timer pin is also reset by turning on a pull-down current on this pin. a low-to-high transition on the on pin starts the hotswap operation. a 10 k pull-up resistor connecting the on pin to the supply is recommended. alternatively, an external resistor divider at the on pin can be used to program an undervoltage lockout value higher than the internal uvlo circuit, thereby setting a voltage level at the vcc supply where the hotswap operation is to start. an rc filter can be added at the on pin to increase the delay time at card insertion if the initial timing cycle delay is insufficient. soft start (ss pin) the ss pin is used to determine the inrush current profile. a capacitor should be attached to this pin. whenever the fet is requested to turn on, the ss pin is held at ground until the sense pin reaches a few mv. a cu rrent source is then turned on, which linearly ramps the capacitor up to 1.3v. the reference voltage for the gate linear control amplifier is derived from the soft start voltag e, such that the inrush linear current limit is defined as i limit = v ss / (20 x r sense ). a voltage can also be driven onto the ss pin to clamp the reference at a different level.
adm1177 preliminary technical data rev. prd | page 8 of 16 timer function the timer pin handles several timing functions with an external capacitor, c timer . there are two comparator thresholds: v timerh (0.2 v) and v timerl (1.3 v). the four timing current sources are a 5 a and a 60 a pull-up, and a 2 a and a 100 a pull-down. the 100 a is a non-ideal current source approximating a 7 k resistor below 0.4 v. these current and voltage levels, together with the value of c timer that the user chooses, determine the initial timing cycle time, the fault current limit time, and the hotswap retry duty cycle. gate and timer functions during a hotswap during hot insertion of a board onto a live supply rail at vcc, the abrupt application of supply voltage charges the external fet drain/gate capacitance, which could cause an unwanted gate voltage spike. an internal circuit holds gate low before the internal circuitry wakes up. this reduces the fet current surges substantially at insertion. the gate pin is also held low during the initial timing cycle, and until the on pin has been taken high to start the hotswap operation. during hotswap operation the gate pin is first pulled up by a 12 a current source. if the current through the sense resistor reaches the overcurrent fault timing threshold, voctim, then a pull-up current of 60 a on the timer pin is turned on, and this pin starts charging up. at a slightly higher voltage in the sense resistor, the error amplifier servos the gate pin to maintain a constant current to the load by controlling the voltage across the sense resistor to the linear current limit, v lim . a normal hotswap will complete when the board supply capacitors near full charge and the current through the sense resistor drops, to eventually reach the level of the board load current. as soon as the current drops below the overcurrent fault timing threshold, the current into the timer pin will switch from being a 60 a pull-up to a 100 a pull-down. the adm1177 will then drive the gate voltage as high as it can to fully enhance the fet and reduce r on losses to a minimum. a hotswap will fail if the load current fails to drop below the overcurrent fault timing threshold, v octim , before the timer pin has charged up to 1.3 v. in this case the gate pin is then pulled down with a 2 ma current sink. the gate pull-down will stay on until a hotswap retry starts, which can be forced by de-asserting then re-asserting the on pin, or the device will retry automatically after a cool-down period, on the adm1177- 1. the adm1177 also features a method of protection from sudden load current surges, such as a low impedance fault, when the current seen across the sense resistor may go well beyond the linear current limit. if the fast overcurrent trip threshold, v ocfast , is exceeded, the 2 ma gate pull-down is turned on immediately. this pulls the gate voltage down quickly to enable the adm1177 to limit the length of the current spike that gets through, and also to bring the current through the sense resistor back into linear regulation as quickly as possible. this protects the backplane supply from sustained overcurrent conditions, which may otherwise have caused problems with the backplane supply level dropping too low. calculating current limits and fault current limit time the nominal linear current limit is determined by a sense resistor connected between the vcc and sense pins as given by the equation below: i limit(nom) = v lim(nom) /r sense = 100 mv/ r sense (1) the minimum linear fault current is given by equation 2: i limit(min) = v lim(min) /r sense(max) = 90 mv/ r sense(max) (2) the maximum linear fault current is given by equation 3: i limit(max) = v lim(max) /r sense(min) = 110 mv/ r sense(min) (3) the power rating of the sense resistor should be rated at the maximum linear fault current level. the minimum overcurrent fault timing threshold current is given by i octim(min) = v octim(min) /r sense(max) = 85 mv/ r sense(max) (4) the maximum fast overcurrent trip threshold current is given by i ocfast(max) = v ocfast(max) /r sense(min) = 115 mv/r sense(min) (5) the fault current limit time is the time that a device will spend timing an overcurrent fault, and is given by t fault ~= 21.7 c timer ms/f (6) initial timing cycle when vcc is first connected to the backplane supply, there is an internal supply (time-point (1) in figure 4) in the adm1177 which needs to charge up. a very short time later (significantly less than 1 ms) the internal supply will be fully up and, since the undervoltage lockout voltage has been exceeded at vcc, the device will come out of reset. during this first short reset period the gate pin is held down with a 25 ma pulldown current, and the timer pin is pulled down with a 100 a current sink. the adm1177 then goes through an initial timing cycle. at point (2) the timer pin is pulled high with 5 a. at time point (3), the timer reaches the v timerl threshold and the first portion of the initial cycle ends. the 100 a current source then pulls down the timer pin until it reaches 0.2 v at time
preliminary technical data adm1177 rev. prd | page 9 of 16 point (4). the initial cycle delay (time point 2 to time point 4) is related to c timer by equation: t initial ~= 270 c timer ms/f (7) when the initial timing cycle terminates, the device is ready to start a hotswap operation (assuming on pin is asserted). in the example shown in figure 4, the on pin was asserted at the same time as vcc was applied, so the hotswap operation starts immediately after time-point (4). at this point the fet gate is charged up with a 12 a current source. at timepoint (5) the threshold voltage of the fet is reached and the load current begins to flow. the fet is controlled to keep the sense voltage at 100 mv (this corresponds to a maximum load current level defined by the value of r sense ). at timepoint (6) v gate and v out have reached their full potential and the load current has settled to its nominal level. figure 5 illustrates the situation where the on pin is asserted after v vcc is applied. v vcc v on v gate v out v timer initial timing c y c l e (1) (2) (3) (4) (5) (6) v sense figure 4. start-up (on asse rts as power is applied) v vcc v on v gate v out v timer initial timing c y c l e (1) (2) (3)(4) (5)(6) v sense (7) figure 5. start-up (on asse rts after power is applied) hotswap retry cycle on adm1177-1 with the adm1177-1 the device will turn off the fet after an overcurrent fault, and will then use the timer pin to time a delay before automatically retrying to hotswap. as with all adm1177 devices, on overcurrent fault is timed by charging the timer cap with a 60 a pull-up current, and when the timer pin reaches 1.3 v the fault current limit time has been reached and the gate pin is pulled down. on the adm1177-1, the timer pin is then pulled down with a 2 a current sink. when the timer pin reaches 0.2 v, it will automatically restart the hotswap operation. the cool down period is related to c timer by equation: t cool ~ = 550 c timer ms/f (8) the retry duty cycle is thus given by t fault /(t cool + t fault ) 100% = 3.8% (9)
adm1177 preliminary technical data rev. prd | page 10 of 16 voltage and current readback in addition to providing hot swap functionality, the adm1177 also contains the components to allow voltage and current readback over an i 2 c bus. the voltage output of the current sense amplifier and the voltage on the vcc pin are fed into a 12-bit adc via a multiplexer. the device can be instructed to convert voltage and/or current at any time during operation via an i 2 c command. when all conversions are complete the voltage and/or current values can be read out to 12-bit accuracy in two or three bytes. serial bus interface control of the adm1177 is carried out via the inter-ic bus (i 2 c). this interface is compatible with fastmode i 2 c (400 khz max). the adm1177 is connected to this bus as a slave device, under the control of a master device. identifying the adm1177 on the i 2 c bus the adm1177 has a 7-bit serial bus slave address. when the device is powered up, it will do so with a default serial bus address. the five msbs of the address are set to 10110, the two lsbs are determined by the state of the adr pin. there are four different configurations available on the adr pin which correspond to four different i 2 c addresses for the two lsbs. these are explained in table 4 below. this scheme allows four adm1177 devices to operation on a single i 2 c bus. table 4. setting i 2 c addresses via the adr pin adr configuration address low state 0xb0 resistor to gnd 0xb2 floating (unconnected) 0xb4 high state 0xb6 general i 2 c timing figure 6 and figure 7 show timing diagrams for general read and write operations using the i 2 c. the i 2 c specification defines specific conditions for different types of read and write operation, which are discussed later. the general i 2 c protocol operates as follows: 1. the master initiates data transfer by establishing a start condition, defined as a high to low transition on the serial data line sda while the serial clock line scl remains high. this indicates that a data stream will follow. all slave peripherals connected to the serial bus respond to the start condition, and shift in the next 8 bits, consisting of a 7-bit slave address (msb first) plus a r/w bit, which determines the direction of the data transfer, i.e. whether data will be written to or read from the slave device (0 = write, 1 = read). the peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit, and holding it low during the high period of this clock pulse. all other devices on the bus now remain idle while the selected device waits for data to be read from or written to it. if the r/w bit is a 0, the master will write to the slave device. if the r/w bit is a 1, the master will read from the slave device. 2. data is sent over the serial bus in sequences of nine clock pulses, eight bits of data followed by an acknowledge bit from the slave device. data transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low to high transition when the clock is high may be interpreted as a stop signal. if the operation is a write operation, the first data byte after the slave address is a command byte. this tells the slave device what to expect next. it may be an instruction such as telling the slave device to expect a block write, or it may simply be a register address that tells the slave where subsequent data is to be written. since data can flow in only one direction as defined by the r/w bit, it is not possible to send a command to a slave device during a read operation. before doing a read operation, it may first be necessary to do a write operation to tell the slave what sort of read operation to expect and/or the address from which data is to be read. 3. when all data bytes have been read or written, stop conditions are established. in write mode, the master will pull the data line high during the 10 th clock pulse to assert a stop condition. in read mode, the master device will release the sda line during the low period before the ninth clock pulse, but the slave device will not pull it low. this is known as no acknowledge. the master will then take the data line low during the low period before the 10 th clock pulse, then high during the 10 th clock pulse to assert a stop condition.
preliminary technical data adm1177 rev. prd | page 11 of 16 scl sda start by master 1 9 1 9 a1 a0 r/w 1 d7 d6 d5 d4 d3 d2 d1 d0 1 1 0 0 ack. by slave frame 1 slave address frame 2 command code ack. by slave scl (continued) d7 d6 d5 d4 d3 d2 d1 d0 ack. by slave 1 9 1 9 d7 d6 d5 d4 d3 d2 d1 d0 ack. by slave stop by master frame n data byte frame 3 data byte sda (continued) figure 6. general i 2 c write timing diagram scl sda start by master scl (continued) sda (continued) a1 a0 r/w 1 1 1 0 0 d7 d6 d5 d4 d3 d2 d1 d0 ack. by master frame 1 slave address frame 2 data byte 19 19 ack. by slave 19 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 no ack. ack. by master 19 stop by master frame 3 data byte frame n data byte figure 7. general i 2 c read timing diagram scl scl sda p s t hd;sta t hd;dat t high t su;dat t su;sta t hd;sta t f t r t low t buf t su;sto p s figure 8. serial bus timing diagram
adm1177 preliminary technical data rev. prd | page 12 of 16 write and read operations the i 2 c specification defines several protocols for different types of read and write operations. the ones used in the adm1177 are discussed below. the following abbreviations are used in the diagrams: table 5. i 2 c abbreviations s start p stop r read w write a acknowledge n no acknowledge quick command this operation allows the master check if the slave is present on the bus. this entails the following: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts ack on sda. s slave address wa 12 3 figure 9. quick command write command byte in this operation the master device sends a command byte to the slave device, as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts ack on sda. 4. the master sends the command byte. the command byte is identified by an msb =0. (an msb =1 indicates an extended register write. see next section.) 5. the slave asserts ack on sda. 6. the master asserts a stop condition on sda to end the transaction. s slave address wa a command byte p 12 3 4 56 figure 10. command byte write the seven lsbs of the command byte are used to configure and control the adm1177. details of the function of each bit are provided in table 6. table 6. command byte operations bit default name function c0 0 v_cont set to convert voltage continuously. if readback is at tempted before the first conversion is complete, the adm1177 will ack and return all zeros in the returned data. c1 0 v_once set to convert voltage once. self-clears. i 2 c will nack an attempted read until adc conversion is complete. c2 0 i_cont set to convert voltage continuously. if readback is at tempted before the first conversion is complete, the adm1177 will ack and return all zeros in the returned data. c3 0 i_once set to convert current once. self-clears. i 2 c will nack an attempted read until adc conversion is complete. c4 0 vrange selects different internal attenuation resistor networks for voltage readback. a 0 in c4 selects a 14:1 voltage divider. a 1 in c4 selects a 7:2 voltage divider. with an adc full-scale of 1.902 v, the voltage at the vcc pin for an adc full-scale result is 26.63 v for vrange = 0 and 6.66 v for vrange = 1. c5 0 n/a unused c6 0 status_rd status read. when this bit is set the data byte read back from the adm1177 will be the status byte. this contains the status of the device alerts. s ee table14 for full details of the status byte.
preliminary technical data adm1177 rev. prd | page 13 of 16 write extended byte in this operation the master device writes to one of the three extended registers of the slave device, as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts ack on sda. 4. the master sends the register address byte. the msb of this byte is set to 1 to indicate an extended register write. the two lsbs indicate which of the three extended registers will be written to (see table 7). all other bits should be set to 0. 5. the slave asserts ack on sda. 6. the master sends the command byte. the command byte is identified by an msb = 0. (an msb = 1 indicates an extended register write. see next section.) 7. the slave asserts ack on sda. 8. the master asserts a stop condition on sda to end the transaction. s slave address ra a register address p register data n 12 34 5 6 78 figure 11. command byte write table 8, table 9, and give details of each extended register. table 7. extended register addresses a6 a5 a4 a3 a2 a1 a0 extended register 0 0 0 0 0 0 1 alert_en 0 0 0 0 0 1 0 alert_th 0 0 0 0 0 1 1 control table 8. alert_en register operations bit default name function 0 0 en_adc_oc1 enabled if a single adc conversion on the i chan nel has exceeded the threshold set in the alert_th register 1 0 en_adc_oc4 enabled if four consecutive adc conversions on the i channel have exceeded the threshold set in the alert_th register 2 1 en_hs_alert enabled if the hotswap has either latched off, or entered a cool down cycle, because of an overcurrent event 3 0 en_off_alert enable an alert if the hs operation is turned off by a transition which de-asserts the on pin, or by an operation which writes the swoff bit high. 4 0 clear clears the on_alert, hs_alert and adc_alert sta tus bits in the status register. these may immediately reset if the source of the alert has not been cleared, or disabled with the other bits in this register. this bit self-clears to 0 after the status register bits have been cleared. table 9. alert_th register operations bit default function 7:0 ff the alert_th register sets the current level at which an alert will occur. defaults to adc full-scale. alert_th 8-bit number corresponds to the top 8-bits of the current channel data. table 10. control register operations bit default name function 0 0 swoff force hotswap off. equivalent to de-asserting the on pin.
adm1177 preliminary technical data rev. prd | page 14 of 16 read voltage and/or current data bytes the adm1177 can be set up to provide information in three different ways (see write command byte section above). depending on how the device is configured the following data can be read out of the device after a conversion (or conversions): 1. voltage and current readback. the adm1177 will digitize both voltage and current. three bytes will be read out of the device in the following format: table 11. byte contents b7 b6 b5 b4 b3 b2 b1 b0 1 voltage msbs v11 v10 v9 v8 v7 v6 v5 v4 2 current msbs i11 i10 i9 i8 i7 i6 i5 i4 3 voltage lsbs v3 v2 v1 v0 i3 i2 i1 i0 2. voltage readback . the adm1177 will digitize voltage only. two bytes will be read out of the device in the following format: table 12. byte contents b7 b6 b5 b4 b3 b2 b1 b0 1 voltage msbs v11 v10 v9 v8 v7 v6 v5 v4 2 voltage lsbs v3 v2 v1 v0 0 0 0 0 3. current readback . the adm1177 will digitize current only. two bytes will be read out of the device in the following format: table 13. byte contents b7 b6 b5 b4 b3 b2 b1 b0 1 current msbs i11 i10 i9 i8 i7 i6 i5 i4 2 current lsbs i3 i2 i1 i0 0 0 0 0 the following series of events occur when the master receives three bytes (voltage and current data) from the slave device: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the read bit (high). 3. the addressed slave device asserts ack on sda. 4. the master receives the first data byte. 5. the master asserts ack on sda. 6. the master receives the second data byte. 7. the master asserts ack on sda. 8. the master receives the third data byte. 9. the master asserts no ack on sda. 10. the master asserts a stop condition on sda and the transaction ends. for the cases where the master is reading voltage only or current only, only two data bytes will be read and events 7 and 8 above will not be required. s slave address ra a data 1 a p data 2 n 12 34567 8910 data 3 figure 12. three byte read fromadm1177 s slave address ra a register address p register data n 12 34 5 6 78 figure 13. two byte read fromadm1177 read status register a single register of status data can also be read from the adm1177. 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the read bit (high). 3. the addressed slave device asserts ack on sda. 4. the master receives the status byte. 5. the master asserts ack on sda. s slave address ra a data 1 12 345 figure 14. status read fromadm1177 table 14 shows the adm1177 status registers in detail. note that bits 1, 3 and 5 are cleared by writing to bit 4 of the alert_en register (clear).
preliminary technical data adm1177 rev. prd | page 15 of 16 table 14. status byte operations bit name function 0 adc_oc an adc based overcurrent comparison ha s been detected on the last 3 conversions 1 adc_alert an adc based overcurrent trip has happened, which has caused the alert. cleared by writing to bit 4 of the alert_en register. 2 hs_oc the hotswap is off due to an analog overcurrent event. on parts which latch off, this will be the same as the hs_alert status bit (if en_hs_alert=1). on the retry parts this will in dicate the current statea 0 could indicate that the data was read during a period when the device is retrying, or th at it has successfully hotswapped by retrying after at least one overcurrent timeout. 3 hs_alert the hotswapper has failed since th e last time this was reset. cleared by wr iting to bit 4 of the alert_en register. 4 off_status the state of the on pin. set to 1 if the input pin is de-assert ed. can also be set to 1 by writing to the swoff bit of the control register. 5 off_alert an alert has been caused either by the on pin or the swoff bit. cleared by writing to bit 4 of the alert_en registe r. kelvin sense resistor connection when using a low-value sense resistor for high current measurement the problem of parasitic series resistance can arise. the lead resistance can be a substantial fraction of the rated resistance making the total resistance a function of lead length. this problem can be avoided by using a kelvin sense connection. this type of connection separates the current path through the resistor and the voltage drop across the resistor. figure 15 below shows the correct way to connect the sense resistor between the vcc and sense pins of the adm1177. sense resistor kelvin sense traces current flow to load current flow from supply v cc sense adm1177 figure 15. kelvin sense connections
adm1177 preliminary technical data rev. prd | page 16 of 16 outline dimensions 0.0197 (0.50) bsc 0.122 (3.10) 0.114 (2.90) 10 6 5 1 0.199 (5.05) 0.187 (4.75) pin 1 0.122 (3.10) 0.114 (2.90) 0.012 (0.30) 0.006 (0.15) 0.037 (0.94) 0.031 (0.78) seating plane 0.120 (3.05) 0.112 (2.85) 0.043 (1.10) max 0.006 (0.15) 0.002 (0.05) 0.028 (0.70) 0.016 (0.40) 0.009 (0.23) 0.005 ( 0.13 ) 6 0 o 0.120 (3.05) 0.112 (2.85) o figure 16. 10-lead msop package (rm-10) dimensions shown in millimeters ordering guide model hotswap retry option brand temperatur e range package description package outline ADM1177-1ARMZ-R7 automatic retry version m5y ?40c to +85c msop-10 rm-10 adm1177-2armz-r7 latched off version m5z ?40c to +85c msop-10 rm-10 1 z = pb-free part. ? 2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners.

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